Package

Fault isolation & visualization solutions

 

 

 

Innovative package control solution to face miniaturization/ Increase complexity/ and new processes

  • See through complexity with highest resolution – even with large device
  • The new fault localization solution for advanced sensitivity requirement & beyond
  • From package opening to Metrology to control your access to silicon

Package Miniaturization, Increased Complexity (3D, SiP), and new processes ( TSV, flip chip)

Packaging is facing miniaturization challenges & introduction of more complexity (having multiple component in chip, having 3D), and new processes (Flip chip & TSV). Providing quality requires controlling the failure modes – facing new characterization challenges.

Whereas miniaturization may rely on ‘higher resolution’ needs to identify standard failure mode like crack, solder issue, voids in balls, short in wires; complexity is introducing new challenges in the methodologies requires for package quality control and failure analysis. In addition, new technique use bring new technical challenges, like stress on flip chip.

Challenges are impacting all characterization techniques:

-          Vizualization techniques – can you still visualize all critical wiring/ bonding through 2D visualization?

-          For Flip Chip and MEMS, how do you measure bow & warp through Silicon and Glass

-          Fault detection at package level, do you have resolution/ sensitivity challenges with standard methodologies ( SAM and Liquid Crystal)?

  • From PCB 3D advanced integration to 3D package (flip chip), can electrical test ensure fault localization?

New characterization techniques to be considered

Sector Technologies offers innovative solutions to ensure your Package’s Quality:

 


 

 

package-fault-isolation

  • Highest sensitivity fault localization for package and a THERMAL mapping solution- Fault localization can now be done thanks to electrical activation through packages
    • Detecting your low resistive defects – through package till silicium
    • Enabling z localization/ die localization
    • Enable thermal characterization of your package
      • Check our DCG’s ELITE products

 

 


 

 

TeraHertz TDR

  • Whereas standard electrical Time Domain Reflectometry ( TDR) is limited fault localisation resolution down to mm range, TeraHertz is enabling resolution down to 10µm.
    • Detecting your open defects in packages
      • Check our TeraView’s EOTPR products

 


 

  • Localize & Vizualize DENSER packages, with the HIGHEST resolution for your larger packages - Ensuring Non Destructive solution.
    • Standard Xray 2D is now limited in ensuring correct inspection of the most advanced packages
    • Xray 3D computed tomography is now required to see "hidden" structures
    • Highest resolution 3D to resolve defect structures
    • Your samples are big - this is a limit to ensure resolution with conventional Xray technology
    • Please check why the Xradia products is different from conventional 3D Xray CT (computed tomography) - ensuring your 3D resolutions ACROSS sample size

 


Package Opening

 

 

 

or

Check on JetEtch or FA-LIT products from Nisene Technology

Package

Fault isolation & visualization

Innovative package control solution to face miniaturization/ Increase complexity/ and new processes

Ø See through complexity with highest resolution – even with large device

Ø The new fault localization solution for advanced sensitivity requirement & beyond

Ø bow, warp control for wafers/ flip chip process

Package Miniaturization, Increased Complexity (3D, SiP), and new processes (TSV, flip chip)

Packaging is facing miniaturization challenges & introduction of more complexity (having multiple component in chip, having 3D), and new processes (Flip chip & TSV). Providing quality requires controlling the failure modes – facing new characterization challenges.

Whereas miniaturization may rely on ‘higher resolution’ needs to identify standard failure mode like crack, solder issue, voids in balls, short in wires; complexity is introducing new challenges in the methodologies requires for package quality control and failure analysis. In addition, new technique use bring new technical challenges, like stress on flip chip.

Challenges are impacting all characterization techniques:

- Vizualization techniques – can you still visualize all critical wiring/ bonding through 2D visualization?

- For Flip Chip and MEMS, how do you measure bow & warp through Silicon and Glass

- Fault detection at package level, do you have resolution/ sensitivity challenges with standard methodologies (SAM and liquid Crystal)?

o From PCB 3D advanced integration to 3D package (flip chip), can electrical test ensure fault localization?

New characterization techniques to be considered

Sector Technologies offers innovative solutions to ensure your Package’s Quality:

Ø Bow, Warp and full Topography measurements for Silicon, flip-chip or glass

o Check our Variometric or VarioProfile solution to enable measurement through Silicon and glass solution

Ø The electrical fault localization for package – a real 3D ENABLER – a THERMAL mapping solution

o Detecting your low resistive defects – through package till silicium

o Enabling z localization/ die localization

o Enable thermal characterization of your package

§ Please check our DCG’s ELITE products

Ø Vizualize denser packages, with the highest resolution for your larger packages - Ensuring Non Destructive solution

o Please check why the Xradia products solution is not “just rotating” your package



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